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C8051F380/1/2/3/4/5/6/7/C
22. SMBus0 and SMBus1 (I 2 C Compatible)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I 2 C serial bus. The
C8051F380/1/2/3/4/5/6/7/C devices contain two SMBus interfaces, SMBus0 and SMBus1.
Reads and writes to the SMBus by the system controller are byte oriented with the SMBus interface auton-
omously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system
clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the
system clock used). A method of extending the clock-low duration is available to accommodate devices
with different speed capabilities on the same bus.
The SMBus may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration
logic, and START/STOP control and generation. The SMBus peripherals can be fully driven by software
(i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recogni-
tion and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the
SMBus0 peripheral and the associated SFRs is shown in Figure 22.1. SMBus1 is identical,with the excep-
tion of the available timer options for the clock source, and the timer used to implement the SCL low time-
out feature. Refer to the specific SFR definitions for more details.
SMB0CN
M T S S A A A S
A X T T C R C I
S M A O K B K
SMB0CF
E I B E S S S S
N N U X M M M M
S H S T B B B B
T O
E D
R E
R L
Q O
S
T
M
B
Y H T F C C
O O T S S
L E E 1 0
D
00
01
10
11
T0 Overflow
T1 Overflow (SMBus0) or T5 Overflow (SMBus1)
TMR2H Overflow
TMR2L Overflow
Interrupt
SMBUS CONTROL LOGIC
Arbitration
FILTER
SCL
IRQ Generation
Request
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
Hardware ACK Generation
Data Path
Control
SCL
Control
SDA
Control
N
C
R
O
S
S
B
Port I/O
A
R
SMB0DAT
7 6 5 4 3 2 1 0
FILTER
SDA
S
L
V
6
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
S G
L C
V
0
S S S S S S S
L L L L L L L
V V V V V V V
M M M M M M M
E
H
A
C
6 5 4 3 2 1 0
K
SMB0ADR
SMB0ADM
N
Figure 22.1. SMBus Block Diagram
Rev. 1.4
205
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